1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
In general, semiconductor memory devices are broadly a classified into volatile memories such as an RAM and non-volatile memories such as an ROM. The non-volatile memories are broadly classified into DRAMS and static random access memories (SRAMs). Non-volatile memories are broadly classified into a mask ROM, an EPROM, a flash memory, an EEPROM and a fuse ROM. Since the DRAM stores data by accumulating electric charges in a cell capacitor, it requires a refresh operation. However, memory cells have a simple structure. Therefore, DRAMs having a large-scale memory capacity can be formed with a low cost.
The memory cell of DRAM is generally formed of a transfer gate formed of an N-channel MOS transistor and a cell capacitor. The transfer gate is connected between a bit line and a cell capacitor, and has a gate electrode connected to a word line. When the potential of word line rises, the transfer gate is turned on. Thereby, electric charges accumulated in the cell capacitor flow onto the bit line via the transfer gate in the read operation, and the electric charges on the bit line flow into cell capacitor via the transfer gate in the write operation. Therefore, the memory cell holds binary data of xe2x80x9c0xe2x80x9d (logical low) or xe2x80x9c1xe2x80x9d, (logical high) in accordance with the state of potential in cell capacitor.
Since the DRAM is generally formed on a silicon substrate, xcex1-particles emitted from a material of interconnection or the like are injected into the silicon substrate, so that data stored in the cell capacitor may be inverted. Thus, a so-called soft error may occur. Meanwhile, further increase of the degree of integration of DRAMs has been desired, and it is now expected that DRAMs having a large-scale storage capacity such as 256 Mbits or 1 Gbit will be mass-produced in a near future. In order to improve the degree of integration of DRAM, it is generally necessary to reduce the gate length. However, reduction of the gate length remarkably causes a short channel effect, so that the gate length can be reduced only to a limited extent.
In view of the foregoing, a DRAM may be formed on an SOI substrate including an insulating layer buried in a semiconductor substrate.
In the DRAM formed on the SOI substrate, a body region of a transfer gate forming a memory cell is electrically floated. Here, the body region is a region located between a source region and a drain region of the transfer gate. The body region corresponds to a bulk silicon substrate itself in a conventional DRAM formed on the bulk silicon substrate.
FIG. 67 shows capacity coupling with respect to the body register in a memory cell and its peripheral portion. Referring to FIG. 67, a node 1 of a word line is coupled to a node 4 of a body region via a gate capacity Cg. A node 2 of a bit line is coupled to node 4 of the body region via a parasitic capacity Cd which is necessarily formed at a PN junction region. A node 3 of a cell plate is coupled to body region 4 via a cell capacity Cs. Cell capacity Cs also includes parasitic capacities between the body region and source/drain regions of the transfer gate. The semiconductor substrate is connected to the body region via an insulating layer buried in the semiconductor substrate, so that a capacity Cbg is formed between the semiconductor substrate and the body region in accordance with a potential Vsub of the semiconductor substrate. Therefore, the semiconductor substrate is coupled to body region 4 via capacity Cbg. In FIG. 67, Vwl indicates the potential of word line. Vbit indicates the potential of bit line. Vcp indicates the potential of cell plate.
As described above, the body region is electrically floated and is coupled to the bit line via parasitic capacity Cd. In the unselected memory cells, therefore, such a problem may arise that electric charges of cell capacitors leak through the transfer gates. More specifically, in the read or write operation, potential Vbit of bit line rises from an intermediate potential of (Vccs+Vss)/2, which will be expressed as xe2x80x9cVcc/2xe2x80x9d hereafter, to a power supply potential Vcc. Such variation of the potential of bit line is transmitted to the body region via parasitic capacity Cd, so that a potential Vbody of the body region rises only AV as shown at (b) in FIG. 68. The SOI device is generally designed and manufactured such that capacity Cbg may be small in order to suppress the influence by the substrate potential. If the capacity Cbg is significantly smaller than any one of capacities Cg, Cd and Cs, xcex94V can be expressed by the following formula.
xcex94V=(xc2xd)Vccxc2x7Cd/(Cd+Cg+Cs)
If potential Vbody of the body region of transfer gate rises as described above, the substrate effect reduces its threshold voltage, which promotes flow of the subthreshold current. Therefore, leak through the transfer gate tends to change the potential state of cell capacitor. This results in a high possibility of breakage of data.
An object of the invention is to provide a semiconductor memory device formed on an SOI substrate, in which a leak current in an unselected memory cell is reduced.
Another object of the invention is to provide a semiconductor memory device formed on an SOI substrate, in which noise interference between bit lines is suppressed.
Still another object of the invention is to achieve the foregoing objects with a minimum layout area.
According to an aspect of the invention, a semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in a row direction on the SOI substrate. The plurality of bit line pairs are disposed in a column direction on the SOI substrate. The plurality of memory cells are disposed on the SOI substrate and each are provided correspondingly to any one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a first transistor. The first transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The first transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential. The first transistors in the plurality of memory cells each include a source region, a drain region and a body region located between the source and drain regions. The body regions of the first transistors in the plurality of memory cells are connected to the plurality of body fixing lines.
Preferably, the plurality of body fixing lines are disposed along the plurality of bit line pairs. More preferably, the plurality of body fixing lines are formed at the same layer as the plurality of bit line pairs. Further preferably, the plurality of memory cells are arranged such that the body regions of the first transistors of two of the memory cells are connected to one position of one of the plurality of body fixing lines.
According to the semiconductor memory device, since the body region of the transistor in the memory cell is connected to the body fixing line, the body region is supplied with a predetermined potential. Thereby, the body region is electrically fixed, so that it is possible to prevent change of the potential state of the cell capacitor in the unselected memory cell which may be caused by the leak through the transistor. In the preferred aspect, since the body fixing line is disposed along the bit line pair, the bit line is shielded by the body fixing line. This suppresses noise interference between the bit lines. In the more preferable aspect, since the body fixing line is formed at the same interconnection layer as the bit line pair, noise interference between the bit lines is further suppressed. In the further preferred aspect, since the body regions of the transistors in the two memory cells are connected to one position of the one body fixing line, increase of a layout area is suppressed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.